Memory devices such as EEPROM, flash, and dual bit (such as MONOS EEPROM) or multi-bit memory include a plurality of nonvolatile memory cells. Each memory may include multiple sub-arrays of columns and rows of memory cells. Each memory cell may have a control gate, a floating gate to store charges, a drain and a source, and the ability to erase, program, and read data in a single memory cell or operate on a predetermined block of memory cells. A memory device includes an array of memory cells for the storage of data, a control circuit for handling the input, output, and storage of data, and a reference cell array for reading the logic value of memory cells. The EEPROM or flash memory is used as a built-in memory within products such as microcomputers, personal digital assistants, phones, external storage devices, and within a variety of other products.
A row of memory cells is typically addressed using a word line. A column of memory cells has at least one conductive bit line selectively coupled to a corresponding memory cell in a column for transferring data to single or multiple memory cells. In one example, a column of memory cells may also be coupled to additional bit lines to transfer data from at least one selected memory cell to another memory cell. In another example, for SRAM, local bit lines are typically arranged in bit line pairs, with one bit line being the complement of the other.
A flash MOS transistor includes a source, a drain, a floating gate, and a control gate connected to a word line (WL). Generally, all of the memory cells in a word line row must be selected. A decoder would select one row by selecting a word line while all other word lines are unselected. The drains of the memory cells in a column are connected to bit lines, and the sources of the cells in one row are connected together. Generally, the word line decoder supplies one word line with a select voltage, while applying an override voltage to all other unselected word lines within a block.
Many memory devices address a single memory cell. Alternately, as shown in FIG. 1, a MONOS EEPROM structure has a dual-bit arrangement. Dual bit memory cell 29 has a control gate (CGm) 22 and floating gate memory cells 25a, 25b. The control gate 22 is coupled to a left memory cell 25a and a right memory cell 25b. Common to both right and left memory cells 25a, 25b is a bit line (BLm) 23. With a bit line 23 connected to two memory cells 25a, 25b, both cells may be programmed and read in a single program and read operation. The right and left memory cells 25a, 25b, are correspondingly coupled to word line devices 24a, 24b. 
Various voltages are applied to a memory cell 25a, 25b to program and erase the memory cell as a logic 1 or a logic 0 value respectively. A typical flash memory cell 25a, 25b is programmed by inducing a hot electron injection from the channel region into the floating gate of the MOS transistor. Erasure of a memory cell 25a, 25b is typically performed using Fowler-Nordheim tunneling operation between the floating gate and the source, or between the floating gate and the substrate. Either programming or erasure of a flash cell results in a non-volatile threshold voltage in a programmed or erased cell.
When applying programming voltages, word line devices 24a, 24b are used to create a circuit path to the floating gate of a memory cell 25a, 25b. Various voltages applied to a control gate 22 in combination with bit line 23 and word line 21 are used to program or erase the right and left components 25a, 25b. Other memory cells are similarly programmed or erased, such as CGm−1, CGm+1 when actuating BLm−1, 28 and BLm+1 29. EEPROM memory cells are arranged in an array of rows and columns and may be connected in various configurations. Generally, the conductive interconnections of control gates CGm−1, CGm, CGm+1, . . . and bit lines BLm−1, BLm, BLm+1, . . . are arranged in columns. Word line 21 is coupled to a plurality of memory cells by interconnects that are usually arranged in rows.
Voltages are normally applied via local bit lines, word lines and control gates to read and/or program a memory transistor. Each of the two memory cells 25a, 25b are connected to a bit line (BLm) 23. Word lines are normally deactivated, or held at a low voltage, for example at or below 0.7 volts. To program a target memory transistor 25a, an associated word line (WL) 21 is activated, for example at or above 1 volt, which allows select transistors 24a, 24b to be in a conducting state. An associated control gate (CGm) 22 is activated or selected while adjacent control gates (CGm+1) and (CGm−1) are held in an over-ride (inactive) state. A high voltage, such as 4.5 volts, is applied to an associated bit line (BLm) 23, and a low voltage, 0 volts, is applied to one adjacent bit line (BLm−1) 28. Select transistor 24a is in a conducting state, providing program current to flow to memory transistor 25a. An inhibit voltage, such as 1 volt, is applied to another adjacent bit line (BLm+1) 29 and select transistor 24b is held in a non-conducting state, with no programming current applied to memory transistor 25b. Also, with control gates (CGm+1) and (CGm−1) held in an over-ride state, adjacent memory transistors 26b, 27a are not programmed.
An arrangement of memory cells within a memory device may include memory array partitions with local bit lines in close proximity to and coupled to each memory array partition. Master bit lines are correspondingly coupled to the local bit lines. Local bit lines add capacitance to the overall bit line layout, and so each local bit line will be coupled to the master bit line via decode circuitry, interface circuitry, or a transistor switch. Local select signals control the coupling of a local bit line to a master bit line. U.S. Pat. No. 5,457,647 to McClure describes a hierarchical or two-level bit line configuration such that a number of local bit lines are connected to a master bit line through interface circuitry. Local select signals, when set to the appropriate voltage level, couple a local bit line to the master bit line. Coupling or isolating a local bit line to/from a master bit line controls the overall bit line capacitance to improve the speed of the memory device.
FIG. 2 illustrates a prior art circuit 10 that may be used to erase, program, read, and verify a dual bit programmable memory array 20. A memory array 20 having rows and columns of memory cells may be a single array or an array segment that is a portion of a programmable memory device. A memory device may contain a plurality of memory array segments. Main bit lines 30 MBL0-MBLN continuously run the entire length of a memory array device. Coupled to the memory array 20 are word lines 21 WL0-WLN, control gate lines 22 CG0-CGn, and local bit lines 23 BL0-BLN. A local bit line 70 is coupled to or isolated from a main bit line 30 by a local bit line select transistor 71 and a main bit line isolation transistor 31. A separate path is used to pass high-voltage to local bit lines 23 for an erase or program operation. Generally, two main bit lines 30 and one local bit line 23 are used to perform operations on a pair of memory cells. The two main bit lines 30 are used to sense or drive data from and to the memory cells, while the local bit line 23 is used to supply the proper bias voltage Vbl to the memory cells. A main bit line 30 is normally isolated from a local bit line 70 when applying bias voltages to a memory cell in the memory array 20 by a main bit line isolation transistor 31. A voltage bias line 60 Vbl may apply a bias voltage to the bit lines 23 by activating a voltage isolation transistor 61. Operations may be performed on memory cells in the memory array 20 by activating a plurality of select devices such as a select transistor 41 when activating a sense circuit 40, or a programming circuit 40.
When a bias voltage Vbl is applied to a local bit line 70, the local bit line 70 must only carry enough current to program up to two memory bits in the memory array segment 20. However, the bias voltage line 60 must be capable of carrying enough current for all of the bits in the memory array segment 20. The width of the voltage bias line 60 must therefore be capable of carrying a high amount of current. The width of each voltage bias line 60 therefore becomes a critical factor for high-capacity high-density memory array.
Main bit lines 30 generally run the length of an entire memory device including running to multiple partitions within a memory device. Long bit lines present a larger capacitance to sense amplifiers so isolation devices and local bit line select devices must be included for every memory array segment. In many designs, local bit lines 70 are developed in one interconnect layer, with main bit lines 30 developed in another interconnect layer. Local bit lines 70 may be developed, for example, in polysilicon or in metal.
The capacitance of the overall bit line layout (main and local bit lines) is reduced by isolating the local bit lines 70 from the main bit lines 30. It is possible that the performance of a memory device may be improved by reducing the capacitance or leakage of the main bit lines.